(1) Field of the Invention
The invention relates to an operational transconductance amplifier, and more particularly, to an operational transconductance amplifier with improved slew rate through the use of a novel, non-linear current mirror.
(2) Description of the Prior Art
Operational amplifiers are a basic building block in many useful electronic circuits. Operational amplifiers provide signal buffer, gain, feedback and signal processing functions in many integrated circuit designs. Designing an operational amplifier requires optimization and tradeoff of several operating parameters. Slew rate, standby or bias current, stability, and frequency response are parameters that are important in a design optimization.
Referring now to FIG. 1 a typical prior art MOS operational transconductance amplifier circuit is shown. A differential pair is used for the input stage. The differential pair comprises the MOS n-channel, or NMOS, transistors, N2122 and N2226. The differential pair is current biased from a single current source implemented as the NMOS device, N2330. N23 is biased from a bias voltage, VB, that establishes a constant current bias, IB.
The differential pair N21 and N22 gate inputs are coupled to the inverting input, VINxe2x88x92, and the non-inverting input, VIN+, respectively. The key to operation is that the differential pair will translate differences between the inverting and non-inverting input voltages into differences in the first differential current, I1, and the second differential current, I2. Neglecting the effect of offset voltage, when VINxe2x88x92 and VIN+ are the same voltage, then I1=I2=IB/2. When VINxe2x88x92 exceeds VIN+, then I1 greater than I2. Conversely, when VINxe2x88x92 is less than VIN+, then I1 less than I2. The voltage-to-current (transconductance) conversion gain represented by the differential pair is usually large, often on the order of about 50.
The first differential current, I1, is mirrored using the PMOS transistors P2134 to P2342. I1 is then mirrored to from the PMOS device P2342 down to the device using N2446. Finally, output device N2554 mirrors I1 to the output signal, VOUT, to drive the load, CL 18. N2554 made be made larger than N2446 to multiply the first differential current, I1, to create the output current, IOUTN. The second differential current, I2, is likewise mirrored to the output transistor, P2450, using P2238 and may be multiplied to create IOUTP.
In the prior art circuit, the output stage is a push-pull configuration output of type Class AB. In this type of output, the signal is driven from the high side, or power supply (Vcc 10), by an active device and to the low side, or ground 14, by another active device. Further, when the device is at either rail, that is, the power supply or ground, the output current from the power supply to ground is kept to a minimum since one of the complimentary output devices is OFF.
Referring now to FIG. 2, a typical slew rate response for an operational amplifier is shown. The slew rate is a measure of how fast the operational amplifier can switch the output from one rail to the other in response to a step function input. This is a critical parameter in systems, such as switch capacitor circuits, where the amplifier must rapidly drive a large capacitive load. For example, a step function input, Vin 70, occurs at time=to. A small signal analysis of the operational amplifier circuit shows a predicted response, Vop 74, to such a step function wherein the output rises exponentially to about Vcc at time=t1. However, the actual measured response is Voa 78 where the output rises linearly to about Vcc at the much slower time of t2. The reason for the slower response is that the step function represents a large signal change in circuit state that requires the charging and/or discharging of circuit capacitance that must be accomplished using the available bias current. In this case, the operational amplifier is said to be slew rate limited by the available bias current.
To increase the slew rate of the circuit, the bias current may simply be increased. However, in low power applications, the operational amplifier may have a very low budgeted current. In this case, it is not possible to arbitrarily increase the bias current. Prior art approaches to increase the load current-to-bias current ratio, and to thereby increase the slew rate, are stable only over a narrow range of load capacitance. Conversely, operational transconductance amplifiers with dynamic biasing typically have a fixed the load current-to-bias current ratio and are, therefore, not suitable for low current applications.
Several prior art inventions describe operational amplifiers and methods of improving slew rate. U.S. Pat. No. 5,223,753 to Lee et al discloses an operational amplifier having a circuit increase the slew rate without adding to current consumption. An inverted, inverter comprising an NMOS transistor and a PMOS transistor is added between the differential pair stage and the output stage. U.S. Pat. No. 5,515,003 to Kimura teaches a high slew rate operational amplifier where additional transistors gates are coupled to the differential pair gates. During switching, the extra transistors control additional current sources that are coupled in to speed up the slew rate. U.S. Pat. No. 5,883,535 to Kato describes a slew rate controllable amplifier. The current source for the differential pair stage is variable and depends upon the magnitude of the voltage difference between the inverting and non-inverting inputs.
A principal object of the present invention is to provide an effective and very manufacturable operational transconductance amplifier.
A further object of the present invention is to provide an operational transconductance amplifier with improved slew rate performance while maintaining a low bias current and excellent stability.
A still further object of the present invention is to provide an improved operational transconductance amplifier by creating an output stage with improved slew rate and low bias current.
Another still further object of the present invention is to provide a non-linear current mirror output stage with a dynamic pole for excellent stability.
In accordance with the objects of this invention, a non-linear current mirror is achieved. The non-linear current mirror is particularly useful in the output stage of an operational transconductance amplifier for improving slew rate and stability while maintaining low bias current. The non-linear current mirror circuit comprises, first, a first MOS transistor having gate, drain, and source. The gate and drain are coupled together and further coupled to a first current input. A second MOS transistor has gate, drain, and source. The gate is coupled to the first MOS transistor gate, and the drain is coupled to a second current input. A third MOS transistor has gate, drain, and source. The drain is coupled to the second MOS transistor source, and the gate is coupled to the second MOS transistor drain. A fourth MOS transistor has gate, drain, and source. The gate is coupled to the third MOS transistor gate. The source is coupled to the first MOS transistor source and the third MOS transistor source. Finally, the drain forms a current output. The current output value linearly tracks the second current input value over a first range of relative values between the first and second current inputs. The current output is a nonlinear, large value over a second range of relative values between the first and second current inputs.
Also in accordance with the objects of the present invention, an operational transconductance amplifier circuit is achieved. The operational transconductance amplifier exhibits improved slew rate and stability while maintaining low bias current. The circuit comprises, first, a differential pair stage having inputs comprising an inverting input and a non-inverting input, and outputs comprising a first differential current and a second differential current. A push-pull output stage completes the operational transconductance amplifier. The push-pull output stage comprises, first, a low-side, non-linear current mirror having a first current input, a second current input, and a current output. The first current input is coupled to the first differential current, while the second current input is coupled to the second differential current. The current output forms a low-side output for the operational transconductance amplifier. A high-side, non-linear current mirror completes the push-pull output stage. The high-side, non-linear current mirror has a first current input, a second current input, and a current output. The first current input is coupled to the second differential current, while the second current input is coupled to the first differential current. The current output forms a high-side output for the operational transconductance amplifier. The low-side and high-side non-linear current mirrors each comprise, first, a first MOS transistor having gate, drain, and source. The gate and drain are coupled together and further coupled to a first current input. A second MOS transistor has gate, drain, and source. The gate is coupled to the first MOS transistor gate and the drain is coupled to a second current input. A third MOS transistor has gate, drain, and source. The drain is coupled to the second MOS transistor source and the gate is coupled to the second MOS transistor drain. Finally, a fourth MOS transistor has gate, drain, and source. The gate is coupled to the third MOS transistor gate. The source is coupled to the first MOS transistor source and the third MOS transistor source. The drain forms a current output. The current output value linearly tracks the second current input value over a first range of relative values between the first and second current inputs. The current output is a non-linear, large value over a second range of relative values between the first and second current inputs.